Digital VLSI / ASIC Project – Verilog, Synthesis, Gate-Level Simulation & Power Analysis (Cadence)
Engineering Mentor
Digital VLSI / ASIC Project – Verilog, Synthesis, Gate-Level Simulation & Power Analysis (Cadence)
Unknown
- Remote
Negotiable
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I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation... (Budget: ₹1500 - ₹12500 INR, Jobs: ASIC, Circuit Design, Digital Design, Digital Electronics, Electrical Engineering, Electronics, Engineering, FPGA)